Extra Adresses in ASM

[doomkaiber001]

Ok, how would you use two addresses in an ASM code. I now start my code by loading the main address ( e.g ammo)

lis r5, 0x8000
ori r5, r5, 0x0001

Now, what if I was making a code that use two different addresses from totally different areas (like 80B5EF76 and 80FF590F). In the compiler I use, you can only use 1 main address.

Would I use a pointer offset with the first address (r5)?

[wiiztec]

Are you trying to make a C0 code?

[doomkaiber001]

Well, no. In fact, that's new to me!

I was just curious, and would like to see how to do it. Could you also explain the difference between a C2 and C0 code?

[wiiztec]

C2 hooks into an ASM address and writes in a non conditional branch to where your C2 code is stored in RAM then at the end of your C2 code it automatically jumps to the line after the one that was hooked, so C2 codes only run when the original ASM instruction would run

C0 is an ASM code that runs every frame

[doomkaiber001]

Ok, so I think I should leave that until I'm a bit more experienced.

So how would you use two addresses?

[doomkaiber001]

Anyone?

[wiiztec]

I don't get what you mean by two addresses

[dragonboy269]

I think they're mixing it up. There are 2 different "addresses" you could be talking about.
One is the address you set in the compiler, eg 0x80000000
The other addresses are the ones you use in your code, and you can have as many of these as you want.

[doomkaiber001]

But how does
lis r22, 0x8097
ori r22, r22, 0x0001
become an address unless specified in the Main address in the compiler.

Couldn't that just be read as a value of something (Money)? How does the CPU know this is an address?

[dcx2]

You're right, it could be a value, like money.  It could be a floating point value.  It could be four characters from a string.  (well, almost)

The biggest clue that it's an address is the fact that...well...it's a legal MEM1 address.

The CPU will know it's an address, because some instruction after those ones will use r22 in parentheses.  e.g. lbz r3,0(r22).  I used Load Byte and Zero because your address, being odd, is byte-aligned.

If r22 0(r22) does not have a valid address, the CPU will lock up.  If this were Windows, you would probably see something like exception 0xC0000005 - access violation.

EDIT: it's not just r22, but the sum of the offset and r22, that must be a valid memory address.

[doomkaiber001]

Oh! Thank you! I thought you'd use for 80000001 and 80000002;
lwz r22, 1(r5)

(If 80000001 was in r5).

[dcx2]

You shouldn't really do that.  You need to watch out for alignment.

Computers have data stored in various sizes.  We refer to them as a byte (8-bits), half-word (16-bits), or word (32-bits).

If an address reads or writes a word, then it must be word aligned.  That is, the address must be divisible by 4.  So you can't lwz the address 80000001, or 80000002, or 80000003.  But you can 80000000, 80000004, 80000008, etc.

lhz/sth must be half-word aligned; the address should be divisible by 2.  So you can't lhz 80000001, 80000003, 80000005, but you can 80000000, 80000002, 80000004.

lbz/stb can be byte aligned.  That is, the address can be any value.

[doomkaiber001]

Ok, I understand what you have said. I've learnt so much these past few weeks.

[doomkaiber001]

Going back to the C0 Codetype thing, how do you make one? Does it depend on how you start it, or how you write it?

[dcx2]

I think a C0 code might be a bit too much for you right now.  You should really try to write some simple ASM patches; e.g. nop'ing the stw to provide infinite xyz or something similar.  Once you understand how ASM executes, then maybe you could consider writing a C2 code.  Once you can do a C2 code, then maybe you could do a C0 code.

C0 codes are like C2 codes that run in the code handler.  C2 codes are multiple ASM instructions that are executed at a specified address, thanks to some tricky branches that the code handler writes for you.  Simple ASM patches are a single ASM instruction that replaces another.  So you may see why you want to start simpler first.