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« Reply #73 on: June 19, 2012, 01:41:24 PM » 

A little bug I´ve found: If you put a lot of assembly instructions into the compiler, it will miss out zeros in the first line before the lines counter value. The more instructions, the more zeros are left out Try to compile this: Spoiler for Hiden: lwz r5,0(r4)
lis r10, 0x8053 lhz r10, 0x56D2 (r10)
lis r12, 0x9371
cmpwi r10, 0x1000 bne _END
stw r5, 0 (r12) lwz r11, 4 (r4) stw r11, 4 (r12) lwz r11, 8 (r4) stw r11, 8 (r12) lwz r11, 12 (r4) stw r11, 12 (r12) lwz r11, 16 (r4) stw r11, 16 (r12) lwz r11, 20 (r4) stw r11, 20 (r12) lwz r11, 24 (r4) stw r11, 24 (r12) lwz r11, 28 (r4) stw r11, 28 (r12) lwz r11, 32 (r4) stw r11, 32 (r12) lwz r11, 36 (r4) stw r11, 36 (r12) lwz r11, 40 (r4) stw r11, 40 (r12) lwz r11, 44 (r4) stw r11, 44 (r12) lwz r11, 48 (r4) stw r11, 48 (r12) lwz r11, 52 (r4) stw r11, 52 (r12) lwz r11, 56 (r4) stw r11, 56 (r12) lwz r11, 60 (r4) stw r11, 60 (r12) lwz r11, 64 (r4) stw r11, 64 (r12) lwz r11, 68 (r4) stw r11, 68 (r12) lwz r11, 72 (r4) stw r11, 72 (r12) lwz r11, 76 (r4) stw r11, 76 (r12) lwz r11, 80 (r4) stw r11, 80 (r12) lwz r11, 84 (r4) stw r11, 84 (r12) lwz r11, 88 (r4) stw r11, 88 (r12) lwz r11, 92 (r4) stw r11, 92 (r12) lwz r11, 96 (r4) stw r11, 96 (r12) lwz r11, 100 (r4) stw r11, 100 (r12) lwz r11, 104 (r4) stw r11, 104 (r12) lwz r11, 108 (r4) stw r11, 108 (r12) lwz r11, 112 (r4) stw r11, 112 (r12) lwz r11, 116 (r4) stw r11, 116 (r12) lwz r11, 120 (r4) stw r11, 120 (r12) lwz r11, 124 (r4) stw r11, 124 (r12) lwz r11, 126 (r4) stw r11, 126 (r12) lwz r11, 130 (r4) stw r11, 130 (r12) lwz r11, 134 (r4) stw r11, 134 (r12) lwz r11, 138 (r4) stw r11, 138 (r12) lwz r11, 142 (r4) stw r11, 142 (r12) lwz r11, 146 (r4) stw r11, 146 (r12) lwz r11, 150 (r4) stw r11, 150 (r12) lwz r11, 154 (r4) stw r11, 154 (r12) lwz r11, 158 (r4) stw r11, 158 (r12) lwz r11, 162 (r4) stw r11, 162 (r12) lwz r11, 166 (r4) stw r11, 166 (r12) lwz r11, 170 (r4) stw r11, 170 (r12) lwz r11, 174 (r4) stw r11, 174 (r12) lwz r11, 178 (r4) stw r11, 178 (r12) lwz r11, 182 (r4) stw r11, 182 (r12) lwz r11, 186 (r4) stw r11, 186 (r12) lwz r11, 190 (r4) stw r11, 190 (r12) lwz r11, 194 (r4) stw r11, 194 (r12) lwz r11, 198 (r4) stw r11, 198 (r12) lwz r11, 202 (r4) stw r11, 202 (r12) lwz r11, 208 (r4) stw r11, 208 (r12) lwz r11, 212 (r4) stw r11, 212 (r12) lwz r11, 216 (r4) stw r11, 216 (r12)
_END:
cmpwi r10, 0x10 bne _ENDO
lwz r11, 0 (r12) stw r11, 0 (r4) lwz r11, 4 (r12) stw r11, 4 (r4) lwz r11, 8 (r12) stw r11, 8 (r4) lwz r11, 12 (r12) stw r11, 12 (r4) lwz r11, 16 (r12) stw r11, 16 (r4) lwz r11, 20 (r12) stw r11, 20 (r4) lwz r11, 24 (r12) stw r11, 24 (r4) lwz r11, 28 (r12) stw r11, 28 (r4) lwz r11, 32 (r12) stw r11, 32 (r4) lwz r11, 36 (r12) stw r11, 36 (r4) lwz r11, 40 (r12) stw r11, 40 (r4) lwz r11, 44 (r12) stw r11, 44 (r4) lwz r11, 48 (r12) stw r11, 48 (r4) lwz r11, 52 (r12) stw r11, 52 (r4) lwz r11, 56 (r12) stw r11, 56 (r4) lwz r11, 60 (r12) stw r11, 60 (r4) lwz r11, 64 (r12) stw r11, 64 (r4) lwz r11, 68 (r12) stw r11, 68 (r4) lwz r11, 72 (r12) stw r11, 72 (r4) lwz r11, 76 (r12) stw r11, 76 (r4) lwz r11, 80 (r12) stw r11, 80 (r4) lwz r11, 84 (r12) stw r11, 84 (r4) lwz r11, 88 (r12) stw r11, 88 (r4) lwz r11, 92 (r12) stw r11, 92 (r4) lwz r11, 96 (r12) stw r11, 96 (r4) lwz r11, 100 (r12) stw r11, 100 (r4) lwz r11, 104 (r12) stw r11, 104 (r4) lwz r11, 108 (r12) stw r11, 108 (r4) lwz r11, 112 (r12) stw r11, 112 (r4) lwz r11, 116 (r12) stw r11, 116 (r4) lwz r11, 120 (r12) stw r11, 120 (r4) lwz r11, 124 (r12) stw r11, 124 (r4) lwz r11, 126 (r12) stw r11, 126 (r4) lwz r11, 130 (r12) stw r11, 130 (r4) lwz r11, 134 (r12) stw r11, 134 (r4) lwz r11, 138 (r12) stw r11, 138 (r4) lwz r11, 142 (r12) stw r11, 142 (r4) lwz r11, 146 (r12) stw r11, 146 (r4) lwz r11, 150 (r12) stw r11, 150 (r4) lwz r11, 154 (r12) stw r11, 154 (r4) lwz r11, 158 (r12) stw r11, 158 (r4) lwz r11, 162 (r12) stw r11, 162 (r4) lwz r11, 166 (r12) stw r11, 166 (r4) lwz r11, 170 (r12) stw r11, 170 (r4) lwz r11, 174 (r12) stw r11, 174 (r4) lwz r11, 178 (r12) stw r11, 178 (r4) lwz r11, 182 (r12) stw r11, 182 (r4) lwz r11, 186 (r12) stw r11, 186 (r4) lwz r11, 190 (r12) stw r11, 190 (r4) lwz r11, 194 (r12) stw r11, 194 (r4) lwz r11, 198 (r12) stw r11, 198 (r4) lwz r11, 202 (r12) stw r11, 202 (r4) lwz r11, 208 (r12) stw r11, 208 (r4) lwz r11, 212 (r12) stw r11, 212 (r4) lwz r11, 216 (r12) stw r11, 216 (r4)
_ENDO: Zeros are missing... No big deal, though. We can add them in.
